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SDRAMcontrol
- 用VHDL编写的SDRAM控制器,能实现SDRAM的读写控制及片选。-Prepared using VHDL SDRAM controller, able to SDRAM read and write control and chip select.
sdram_control
- 基于硬件语言Verilog的一个sdram控制器的设计以及仿真-Verilog language, a hardware-based controller design and simulation sdram
61EDA_C2442
- ddr sdram控制器的例子,经过了仿真验证,没有问题-ddr sdram
1122
- 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of
ddr_sdr
- DDR SDRAM 控制器 包含测试向量和仿真模型-DDR SDRAM control
FPGA
- 基于FPGA 的SDRAM 控制器的设计方法,使用该方法实现的控制器可非常方便地对SDRAM 进行控制。-FPGA-based SDRAM controller design method, using the method of the controller can easily control the SDRAM.
source
- SDRAM控制器源代码,是ALTERA公司的IP源核,很好很强大-SDRAM controller source code, very very strong
simulation
- SDRAM控制器,ALTEAR公司的IP原核的testbech,很难得-SDRAM controller, ALTEAR' s IP pronuclei testbech, hard to come by
DDR_SDRAM
- SDRAM控制器的相关源程序代码 有需要的同学可以下载-SDRAM controller source code related to students in need can be downloaded
EDAhelper
- 因而,SDRAM常作为数据缓存应用于高速数据传输系统中。目前,许多嵌入式设备的大容量、高速度存储器都采用SDRAM来实现,而且大多都是用专用芯片完成其控制电路,这不但提高了设计成本,而且使系统的硬件电路变得复杂。随着FPGA在嵌入式系统中的广泛应用,如果我们能够结合具体的需要,利用FPGA来设计自己的SDRAM控制器,这些问题就迎刃而解了-During University I studied computer networks have some knowledge about compute
sdram_vhdl
- DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
sdram_access
- sdram 控制器,VHDL程序源代码。-sdram controller,vhdl program
DDR3_user_design
- 在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器,里面生成了Core,可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control
sdram_mdl
- verilog实现SDRAM控制器,quartus工程-verilog SDRAM controller, quartus project
altera_sdram
- 基于quartus平台的sdram控制器设计(verilog 源码)-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
ddr_sdr_latest[1].tar
- ddr sdram 控制器的接口,为工业标准化存储设备提供简单的接口-The DDR SDRAM Controller provides the user with a simplified interface to industry standard memory devices. Using this controller makes accesses to DDR SDRAM devices as simple as possible.
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码,由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
eetop.cn_SDRAM
- 实现sdram控制器的verilog代码,很好的学习资料-The sdram controller verilog code, very good learning materials
sdram_controller
- 该模块是一个基于FPGA的SDRAM控制器,该模块有两个接口,一个接口是系统接口,一个连接SDRAM的接口。可以适应不同速度和带宽的SDRAM。-This application note describes the design of a FPGA SDRAM controller.The controller has a system interface on one side and a SDRAM controller for two 16 MB SDRAMs on the other